The present application relates to a memory apparatus. More particularly, the present application relates to a memory apparatus that can dynamically adjust an array accessing time (tAA).
With the advance of semiconductor manufacturing technologies, the memory capacity of a dynamic memory is correspondingly increasing. The dynamic memory, subject to certain circuitry dimensions, can still provide large storage space for an electronic device that is required for storing a great amount of data.
According to the related art, in order to improve the yield of the conventional dynamic memory, a certain number of normal memory cells complying with the configuration standard of the dynamic memory and a certain number of redundant memory cells are included in the dynamic memory. In the process of testing the dynamic memory, if the normal memory cells are found to be damaged, the redundant memory cells can serve to replace the damaged normal memory cells, and thereby the effective storage capacity of the dynamic memory can be retained.
A redundant device comparator is required for replacing the damaged normal memory cells with the redundant memory cells. In case of reading the data in the redundant memory cells, the required address accessing time cannot be correctly estimated because of the time delay caused by the redundant device comparator. Hence, the address accessing time can merely be obtained by simulation at the design stage. As such, if the address accessing time is overly long, the overall read/write performance of the DRAM will suffer; if the address accessing time is overly short, the erroneous action of accessing the memory apparatus is likely to occur.